Integrator circuit and print quality inspection system embodying the same



Sept. 25, 1962 M. R. CANNON 3,056,032

INTEGRATOR CIRCUIT AND PRINT QUALITY INSPECTION SYSTEM EMBODYING THE SAME 4 SheetsSheet 1 Filed June 50, 1958 OUTPUT 6 E 2/ m n E U m C m m C C 4 9 L R YT 00 E I V 6 A u R T G 1 am EN m D] 30 R T C C E T E M K K N 3 N F F 9 I. R R W .E 0 M E T m T A KNT A M A M AIE R R l D M A l M EMT w v M 5w o 4 2 v R C 2 9 E E E F F U B m R m A m m w m Hm m E n M M 5 A I 9 Sept. 25, 1962 M. R. CANNON 3,056,032

INTEGRATOR CIRCUIT AND PRINT QUALITY INSPECTION SYSTEM EMBODYING THE SAME Filed June 30, 1958 4 Sheets-Sheet 2 l 20 L i l WAVELENGTH-MICRONS RELATIVE SENSITIVITY OF PHOTOCELL (A) TRANSMITTANCE OF FILTER (B) Sept. 25, 1962 M. R. CANNON .3 056 032 INTEGRATOR CIRCUIT AND PRINT QUALITY INSPECTION SYSTEM EMBODYING THE SAME I Filed June 30, 1958 4 Shets-5heet 5 FIG. 3

/0 I00 I l 90 I t A f 1 c 80 I I I 70 I l COMPOSITE RELATIVE RESPONSE (C) WAVELENGTH MICRONS pt 1962 M. RCANNO 3,056,032

INTEGRATOR CIRCUIT AND PRINT QUALITY INSPECTION SYSTEM EMBODYING THE SAME Filed June so, 1958 4 Sheets-Sheet 4- TO UTILIZATIO DEVICE PHOTO ELECTRIC DEV ICE nite States 3,056,032 Patented Sept. 25, 1962 3,056,032 INTEGRATOR ClRCUIT AND PRINT QUALITY INSPECTION SYSTEM This invention relates to apparatus for automatically inspecting a product produced by a high speed machine. More particularly, this invention relates to such an apparatus which is especially well suited for use in inspecting the quality of and detecting defects in the printing on data processing cards.

In the manufacture of data processing cards a continuous web of suitable paper stock is passed into a high speed rotary printing press Where the desired printing is carried out before the individual cards are cut from the web. The form which the printing may take and the quantity of printing may vary from one run to another depending upon the intended use of the cards. It is highly important that the quality of the printing on such data processing cards be maintained above a pre-established minimum because the accuracy and efliciency of transferring data to such cards and the subsequent utilization thereof in a high speed data processing machine requires that the data be marked or located on the data processing cards accurately.

There are various factors which may adversely afiect the printing which is applied to the data processing cards. Variations in the supply of ink constitutes one of the main causes of defective printing. Because of the high speed operation of the printing press considerable wastage occurs unless defects other than those Which are transient in nature are promptly detected and corrected. Of course, transient defects which result in one or a small number of defective cards must also be detected so that the defective cards may be eliminated. Hitherto the cards have been examined in various ways including manual inspection after they were cut from the web. It has also hitherto been proposed to convert light reflected from the cards to an electrical signal and then monitor the electric signal so as to detect printing defects in the cards. In one such arrangement a spot of light was successively swept across the card Width as the freshly printed web moved lengthwise through the illuminated area. In an arrangement for inspecting engraved paper money, it has been proposed to use a rectangular beam whose length is equal to the Width of the material being inspected and to pass the work longitudinally through the inspection or illuminated area so that the Work is exposed to the beam line-by-line with each line having a length equal to the width of the work and having a width equal to the width of the light beam. None of these arrangements are suited for a high speed operation of the type herein contemplated. While such arrangements have various drawbacks perhaps the most serious resides in the extreme difliculty or substantial impossibility to establish the desired degree of sensitivity to defects which require rejection of the work and the required degree of insensitivity to minor imperfections which could be tolerated and did not require rejection.

Data processing cards of the type in connection with which the present invention is outstandingly successful may be formed of paper having any one of nine colors and may be imprinted with ink of any one of six different colors. When a light beam is used to scan such cards in order to inspect the printing thereon and the reflected light is converted to an electrical signal, the relative reflectance of the print and the background formed by the paper surface itself limits the overall sensitivity of the system. In an area where there is no printing, the light reflected from the bare surface of the paper results in a signal which is conveniently designated the blank card signal level. Now, if there is little or no contrast between the amount of light reflected by the blank card and the amount of light reflected from the ink in the printed areas it is diflicult to detect variations in the signal level which result from too much or too little ink in the printed area.

The inspection system contemplated by the present invention provides for the summation or integration of the signal derived from the light reflected from each card area and a comparison is made between the integrated signal and a signal equivalent to or derived from an acceptable card. Provision may be made for rejecting individual cards when the integrated signal derived therefrom differs from the comparison signal by reasonof being too large or too small to an extent which renders it unacceptable.

The variation in the amount of printing applied to different runs of cards through the printing press makes it necessary to set the apparatus at the start of each run. One advantage of the present invention resides in the fact that it may be readily adjusted to take into account the dilference in the signal obtained due to the different print patterns. In a preferred embodiment the adjustment may be readily made so that the integrated signal derived from a good card area of one printing run is the same as that derived from another, even though there is a wide variation in the amount of ink applied tothe cards of the different runs.

The large number of color combinations which may be encountered because of the nine possible paper colors and six ink colors has to a large extent curtailed the usefulness of arrangements heretofore provided for automatically inspecting such data processing cards. An important feature of the present invention resides in the use of a photo-sensitive device which has greater sensitivity to infra red light than to other portions of the spectrum. This takes advantage of the discovery that for all but one of the six possible ink colors in combination with any one of the nine possible paper colors there is a high degree of contrast available due to the wide difference in the spectral reflectance of the blank web material as compared to the spectral reflectance of the inks in the portion of the spectrum ranging in wave length from about 0.7 to 1 micron. Satisfactory response to red ink with any one of the various card stock colors is obtained with a photosensitive device having its peak sensitivity to light having a wave length less than 0.6 micron or about 0.4 to 0.6 micron.

In a preferred embodiment the light from an elongated lamp is passed through a cylindrical lens and a filter so that a long narrow light beam is projected upon the web material coming from the rotary printing cylinder of the press. The length of the light beam is equal to the width of the web material and the motion of the web results in its being continuously scanned longitudinally. Light reflected from the surface of the Web material impinges upon an elongated photocell whose length also corresponds to the Width of the web material. The scanning'rate is determined by the rate at which the web material passes through the illuminated area established by the light beam. Fluctuations in the light impinging upon the photocell result in an electric signal which is amplitied and then passed to an integrator where the impulses derived from a single card area are integrated to provide a signal which reflects the total amount of ink on the individual card area scanned. This signal is fed through a bufler to a comparator network where it is compared to a reference signal which represents the minimum amount of acceptable ink on a card of that type and to a reference signal which corresponds to the maximum acceptable amount of ink. An output from the comparator network is used to actuate a bi-stable device which is switched to either of its two stable conditions depending upon the output from the comparator network. In the system which will be more fully described hereinafter the bi-stable device or trigger is switched to its bad condition at the start of a scanning cycle. At reset time when the entire area of the web which will form one card has been scanned the trigger provides a signal indicative of a bad card unless, prior to reset time, it has been switched to its good condition and remains in this condition for the remainder of the cycle. Thus, in any cycle of operation when the integrator output reaches the minimum acceptance limit the comparator network switches the bi-stable device from its bad to its good card condition. If, before the completion of the scanning of this card, the integrator output reaches the maximum acceptance limit then the bi-stable device is switched back to its bad condition. At reset time, that is when the cut off line of the card area under examination is reached by the scanner, the condition of the bi-sta'ble device determines whether an accept or reject signal is provided.

Further objects as well as advantages of the present invention will be apparent from the following description of a preferred embodiment thereof when read in conjunction with the accompanying drawings in which FIGURE 1 is a view showing diagrammatically a print inspection system constructed in accordance with the present invention;

FIGURE 2 is a graph showing the spectral response of the system when a silicon photovoltaic cell is utilized;

FIGURE 3 is a graph showing the spectral response of the system when a selenium photovoltaic cell is utilized; and

FIGURE 4 is a schematic diagram of the preferred embodiment of the present invention.

Referring now to the drawings in detail, a print inspection system constructed in accordance with the present invention is shown diagrammatically in FIGURE 1 and comprises a lamp having an elongated filament which is preferably projected at reduced width upon the moving paper web 11. Lamp type 190T3/CL is well suited for use in the present system and has a clear quartz envelope with a four inch lighted length helical filament. As shown diagrammatically in FIGURE 1, the light from lamp 10 passes through an elongated cylindrical lens 12 to a filter 13. An elongated photocell 14 is positioned so as to receive light which is only reflected from the area of the web 11 scanned by light beam 15. A lens stop 16 is shown in conjunction with lens 12 which permits suitable focusing of the light beam to provide an illuminated area 0.02 inch in width. Field stops at the edges of the web are used to limit the length of the scan strip.

The light responsive means 14- functions to provide an electrical signal proportional to the instantaneous intercepted radiant energy. Preferably a semi-conductor photo-sensitive device in the form of a silicon photovoltaic cell is utilized. This cell has a peak sensitivity to light having a wave length between 0.8 and 0.9 micron and is used with a filter 13 whose transmittance is sharply peaked for light having a wave length of 0.8 micron to provide a desirable overall response for all the color inks which are normally encountered except red. The spectral sensitivity of the silicon photovoltaic cell is shown by trace A in FIGURE 2 and the spectral transmittance of the filter is shown by trace B in FIGURE 2. With the lamp filament at a temperature of about l890 K. the composite response of the filter and silicon cell is is given by trace C in FIGURE 2. This arrangement provides a desirable degree of contrast between the reflectance of the blank web material and the ink imprinted thereon in a wide range of color combinations. Of the various colors of ink which may be used, all but red has a relatively low degree of reflectance of infrared light having a wave length less than one micron. On the other hand, the various colors of the web materials which normally may be used result in relatively high degree of reflectance of infrared light having a wave length ranging from about 0.7 to 1 micron.

When the web material is imprinted with red ink the desired results are achieved when the composite spectral response of the system is at the blue end of the visible spectrum, that is, below about 0.6 micron. A selenium photovoltaic cell gives desirable results at the blue end of the visible spectrum and even out in the near ultraviolet portion of the spectrum. The relative sensitivity, transmittance and composite relative response of the selenium cell, the filter used therewith and the lamp operating at a temperature of 21 20 K. are shown respectively by traces A, B and C in FIGURE 3. From FIGURE 3 it is apparent that the peak response when the system is utilized to measure the amount of red ink in a card area, falls at about .51 micron, in the blue region of the spectrum, where the reflectance of the card or web material is relatively high compared to that of the red ink.

Referring to the block diagram shown in FIGURE 1, any suitable amplifier 20 is used to step up the relatively low output power of the photocell and the amplified signal is fed to integrator 21 where it is integrated over each card length to provide an indication of the amount of ink in the card area. Except for background noise, which may be due to the mottle of the paper, a blank or unprinted card area provides a zero signal and printed marks in the card area cause signal pulses of amplitude and duration corresponding to the ink density and mark size. The cycle of operation of integrator 21 is synchronized in any convenient manner desired with the movement of the web 11 past light beam 15 so that the integrator is reset, as will be more fully described hereinafter, simultaneously as the trailing cut-off line of the scanned area, indicated at 22 in FIGURE 1, arrives at the light beam.

The output voltage of integrator 21, which is fed through buffer 28 to minimum and maximum comparators 23 and 24, represents at reset time the amount of ink which has been printed on the scanned card area. The integration rate of integrator 21 is adjusted in advance so that it provides a predetermined output voltage for what may be considered as optimum printing quality on a card during a given printing run. At comparator 23 the output voltage from the integrator, through the buffer, is compared to a reference voltage which is representative of the minimum amount of ink necessary to provide an acceptable card. The integrator output voltage is also fed through buffer 28 to comparator 24 where it is compared to a voltage representative of the maximum amount of ink which may be on a card area and yet provide an acceptable card. The output from comparators 23, 24 is fed to bi-stable trigger device 25 which at the start of each cycle is in that one of its two conditions which signals a bad or unacceptable card. The cut-off line of one card area, in the present embodiment, is the start line of the next successive card area. Thus, with the integrator reset to its start condition when the cut-off line is reached it is apparent then that during the initial portion of the scanning cycle for a given card area, the integrator output voltage will, for all acceptable cards and usually for most unacceptable cards, be less than the minimum reference voltage of comparator 23. Sometime during the scan cycle for normal card areas and most bad card areas having excessive ink, the integrator output voltage rises above the minimum reference voltage and trigger 25 is switched to its other or good condition. For normal card areas the integrator output voltage does not reach a value equal to the maximum reference voltage so that at reset time trigger is in its good condition. On the other hand, when the integrator voltage, because an area having an excessive amount of ink is being scanned, increases to or exceeds the maximum reference voltage than the trigger 25 is switched back and is in its bad condition at reset time.

A timing pulse is provided, by means of a photoelectrio device 26 suitably mounted on the printing press, to coincide with the arrival of the cut-off line 22 at the light beam. At the time this timing pulse is received at coincidence circuit 27, the output from comparators 23, 24 reflects the condition of the scanned area and only when the comparator output corresponds to that for a bad card is an output pulse provided by the coincideuce circuit which may be fed to any suitable utilization device which rejects or otherwise disposes of the unacceptable work.

A preferred embodiment of the control circuit of the present system will now be described in greater detail in connection with FIGURE 4. The output from photocell 14, amplified at 2h, is applied to one side of capacitor 30 in such manner that positive pulses represent printing on the card under observation. Thus, the most negative portion of the signal is produced by an unprinted or blank portion of the card. The other side of capacitor 30 is connected through resistor 31 to a suitable source 34 of negative bias voltage, 48 volts, and to the base of a n-p-n type transistor 32 connected as a common collector stage. The common junction of capacitor 3d, resistor 31 and transistor 32 is connected through a clamping diode 33 to a fixed negative voltage source 35, in the present instance -40 volts, whereby the blank card signal level is held at 40 volts and all pulses resulting from printing on the card cause the base of transistor 32 to become more positive than 4() volts. The emitter of transistor 32 is connected to source 35 through a relatively small resistor 36 and a variable resistor 37. The collector of transistor 32 is connected directly to the emitter of an n-p-n type transistor 38 which, as will be more fully pointed out, functions as the integration transistor. The junction of the collector of transistor 32 with the emitter of transistor 38 is connected to ground through a resistor 39 which provides a high impedance to ground.

The emitter of transistor 32 remains substantially at the same potential as its base, thus, the emitter current of transistor 32 is essentially zero for a signal input corresponding to a blank card area and is proportional to the input signal voltage whenever printing is scanned. The collector current of transistor 32 is directly proportional to its emitter current and is equal to the emitter current of transistor 38, being connected directly thereto. It follows, therefore, that the emitter current of transistor 38 is directly proportional to the input signal voltage from amplifier Eli.

Transistor 38 is connected as a grounded base stage, its base being connected directly to bias source 40 of --20 volts and its collector being connected to source 41 of +20 volts through a capacitive load formed by capacitor 42. The output from integrator 21 is taken across capacitor 42 from its junction with the collector of transistor 38. This junction is also connected to buffer 28 and, through a diode 43, to a resetting network comprising a p-n-p type power transistor 44 and a pn-p type driving transistor 45. The emitter of transistor 44 is connected to source 41 and the collector of transistor 44 is connected to the junction of diode 43 and a resistor 46 which is in turn connected to bias source 4%. The base of transistor 44 is connected through a relatively small, current limiting, resistor 47 to the emitter of driver transistor 45. The emitter of transistor is also connected through resistor 48 to a source 49 of about 54-120 volts. The collector circuit of transistor 45 is completed to ground through a resistor 59 having a relatively low value which may be equal to that of re- 'or reference voltages.

sistor 47. The bias for the base of transistor 45 is supplied from source 51 of +24 volts through a resistor 52 while the input is provided through a capacitor 53, a terminal of which is connected to the common junction between resistor 52 and the base.

During normal operation of integrator 21 resistor 48 maintains the emitter base junction of transistor 44 reversely biased and transistor 44 is nonc-onducting. Because of the high back resistance of diode 43 under these conditions, the current of capacitor 42 is equal to the collector current of transistor 38 which in turn is independent of the collector voltage and is proportional to the emitter current of transistor 38. Therefore, the current of capacitor 42 is proportional to the input signal voltage above blank card level received from amplifier '20. The timing pulse from photoelectric device 26 is in the form of a negative voltage pulse and is applied to the base of transistor 45 through capacitor 53. This results in a negative pulse being applied through resistor 47 to the emitter base junction of transistor 44 which is thereby biased in the forward direction to render transistor 44 highly conducting. With transistor 44 highly conductive its collector potential attains a value very close to that of source 41, about +20 volts, and any charge on capacitor 42 is removed through diode 43.

Upon termination of the negative pulse from photoelectric device 26, resistor 46 causes the collector of transistor 44 to be at approximately the voltage of source 40, about 20 volts. Source 40 being equal to but opposite in sign to source 41, its negative voltage reversely biases diode 43 thereby permitting capacitor 42 to recharge in a negative direction according to the input signal from amplifier 2t Resistor 50 in the collector circuit of transistor 45 limits the power dissipation of this transistor when it drives the power transistor 44 to full conduction.

In the present embodiment resistor 37 is a 50,000 ohm potentiometer and adjustment of its slider provides adjustment of the proportionality constant between the charging current of capacitor 42 and the signal voltage applied to transistor 32. When potentiometer 37 is adjusted so that it constitutes a zero resistance, or is removed entirely, a relatively small input signal from amplifier 20 results in a large charging current to capacitor 42. On the other hand, when potentiometer 37 is adjusted to present its full 50,000 ohms in the circuit, even a relatively large input voltage pulse causes a small capacitor charging current. By proper adjustment of potentiometer '37, the integration rate of circuit 21 is controllable to the end that either a fully printed good card of one run or a sparsely printed good card of another run results in the same output voltage appearing at the terminal of the collector of transistor 38 which is the integrator output terminal. This is highly advantageous because the same saw tooth voltage then appears at the integrator output terminal for cards of different runs of the same print quality even though these cards may have widely different amounts of ink imprinted thereon.

The negative-going saw tooth voltage output from integrator 21 is fed to buffer 28 which serves to minimize loading of capacitor 42 and makes it possible to obtain relatively large current at unity voltage gain, i.e., no shift in potential. Buffer 28 comprises a p-n-p transistor 56 and an n-p-n type transistor 57 connected as a double emitter follower. The output, taken at terminal 55, which is connected to the common terminal of the emitter of transistor 57 and its load resistor 58, is applied to two comparatorsv 23 and 24 where it is compared to tolerance In efiect the comparator network together with the trigger circuit 25 compare the tim integral of the signal voltage derived from scanning each succeeding printed card with a voltage which corresponds to the value of a good card. The reference voltages to which the output of integrator 21 is compared provide the desired maximum and minimum ink tolerances.

The voltage comparator networks 23 and 24 each constitutes a regenerative emitter coupled difference amplifier of conventional construction. Comparator 23 comp-rises a p-n-p transistor 63 whose base is connected through one winding 60a of a transformer 60 having three windings to potentiometer 6i; one side of which is grounded and the other side of which is connected to a source 62 of a suitable positive reference voltage, in the present instance five volts. A second winding 6% of transformer 60 which functions as a primary or input winding is connected in the collector circuit of p-n-p type transistor 64. The base of transistor 64 is connected to buffer terminal 55.

As is most clearly shown in FIGURE 4, the comparator network 24 is preferably of identical construction with comparator 23, one winding 66a of transformer 66, also having three windings, being connected between the base of p-n-p type transistor 67 and potentiometer 68, one end of which is connected to ground and the other end of which is connected to a source 69 of a suitable negative reference voltage, in the present instance five volts. A second winding 66b of transformer 66 is connected in the collector circuit of p-n-p type transistor 70, the base of which is also connected to output terminal 55.

Potentiometers 61 and 6% supply plus and minus reference voltages to the respective comparators 23 and 24 which may be adjusted to provide the desired minimum and maximum ink tolerances, respectively. When the negative-going saw tooth voltage from terminal 55 reaches the reference voltage of comparator 23, conduction is transferred from transistor 63 to transistor 64 and an output in the form of a sharp pulse appears in the third winding 66c of transformer 60 of this comparator. As will be more fully pointed out, winding 60c, together with the third winding 660 of the transformer of comparator 24, control the operation of trigger circuit 25. In the event the output from integrator 21 represents the result of the scanning of a bad card having an excessive amount of ink thereon the negative-going saw tooth voltage of terminal 55 reaches the reference voltage of comparator 24 with the result that conduction is transferred from transistor 67 to transistor 70 and a pulse appears in the third winding 660 of transformer 66 which couples comparator 24 to one side of the trigger circuit 25.

Trigger '25 is a conventional bi-stable device in which p-n-p type transistors 73 and 74 are cross-coupled resistively. At the start of a scanning cycle which coincides with the start of an integrating cycle of integrator 21, trigger 25 is in that one of its two stable conditions representing a bad card condition as will be more fully pointed out hereinafter. Transistor 73 is conducting and transistor 74 is turned off.

Coincidence circuit 27 comprises a p-n-p type transistor 77 Whose base is connected through a diode 75 to the collector of transistor 74. The common terminal of the collector of transistor 74 and diode 75 is connected through load resistor 76 to voltage source 44]. The common terminal '78 of the base of transistor 77 and diode 75 is connected through a resistor 79 to voltage source 40 also. Resistor 79 is preferably about times the value of resistor 76. Another diode Si) is connected as indicated between terminal 73 and photoelectric device 26 so as to receive a pulse simultaneously with capacitor 53 of the integrator reset stage. When the negative-going saw tooth voltage from integrator 21 drops to the level of the reference voltage of comparator 23 and an output pulse appears in transformer winding 60c, transistor 73 is turned off and transistor 74 is turned on. This serves to bias diode 75 in its foiward direction. Assuming that a good card is being scanned and the integrator saw tooth voltage output never drops to the level of the reference voltage of comparator 24 then transistor 74 of trigger circuit is conducting upon the arrival of cut-off line 22 at the scanning area. At this time the pulse from photoelectric device 26 is applied to diode 86 to probe the condition of trigger circuit 25 and because diode 75 is conducting in the forward direction, the probe pulse does not appear across load resistor 81 in the collector circuit of transistor 77. In effect the probe pulse is blocked and this is indicative of a good card. On the other hand, if a bad card is being scanned and the integrator output voltage does not drop to the level of the reference voltage of comparator 23 or, having reached this level, continues down to or below the reference voltage of comparator 24 before the scanning of the card area is completed, then transistor 74 is turned off and transistor 73 is turned on at the time of the arrival of the pulse from photoelectric device 26. Under this condition diode 75 is nonconductive and the probe pulse passes on to a suitable utilization device which serves to reject the bad cards.

The pulse from photoelectric device 26 is also utilized to reset trigger circuit 25 to its bad condition, that is, with transistor 73 conducting and transistor 74 turned off. This is accomplished through a delay circuit indicated at 85 which comprises a p-n-p type transistor 86 whose base is connected through capacitor 87 to the common terminal of diode 8t and photoelectric device 26. The common terminal of the base of transistor 86 and capacitor 87 is connected through bias resistor 38 to source 40. The collector of transistor 86 is connected through a relatively small resistor 89 to source 49 and is connected directly through resistor 90 to the common terminal between the base of transistor 73 and transformer Winding 69c. Delay circuit 85 provides sufficient delay before the reset pulse is applied to trigger circuit 25 to permit the latter to gate the probe pulse before trigger circuit 25 is reset to the bad card condition. The effect of delay circuit 85 is to differentiate the trailing edge of the pulse applied to capacitor 87.

As has been described hereinabove, adjustment of potentiometer 37 controls the ratio of the charging current applied to integrator capacitor 42 with respect to the signal voltage obtained from amplifier 20. This may be manually accomplished by applying the output from integrator 21 through a peak reading volt meter 92 to a zero center meter 93. At setup time the operator observes the first new cards turned out by the printing press and when what is considered to be a good or standard card is delivered potentiometer 37 is adjusted until a zero reading is obtained on meter 93. Preferably the adjustment of potentiometer 37 is effected by applying the output from the peak reading volt meter 92 to a normally de-energized servo control 94 which in turn controls a permanent magnet field type D.-C. motor 95 coupled to the slider of potentiometer 37 through a suitable reduction gear. At setup time, when the printing press starts delivering good cards, it is only necessary for the operator to close a switch (not shown) connecting the servo control 94 with peak reading volt meter 92. During normal operation volt meter 93 provides a visual indication of the quality of the printing. If the amount of ink applied to the cards begins to drift, the voltage applied to meter 93 will drift accordingly and this will be reflected in the reading of the meter. While any single poorly printed card results in a corresponding reject signal from coincidence circuit 27, the fact that a single poor card has been scanned does not register on meter 93.

While the present system as shown and described hereinabove provides an output pulse to a utilization device whenever a bad card is scanned and the absence of a pulse is indicative of a good card, the arrangement through to the comparators is fail-safe. That is to say, in the event of a failure in the circuit ahead of the comparators, the bad card signal will be provided to the utilization device. If desired the entire system may be rendered fail-safe by providing an output pulse in the collector circuit of transistor 77 when good cards are scanned and by having the absence of a pulse indicate the bad card condition. This is accomplished by breaking the connection between diode 75 and the common terminal of the collector of transistor 74 with its load resistor 76 and instead connecting this terminal of diode 75 to the collector of transistor 73 at its connection with its load resistor.

It should also be noted that in the preferred embodiment described the reset stage of integrator 21 functions as a switch which closes to shunt capacitor 42 when the pulse from photoelectric device 26 is received and thereby rapidly discharge capacitor 42. It will be recognized that other arrangements may be utilized for resetting the integrator when other effects are desired.

The terms and expressions which have been employed are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described Or portions thereof, but it is rec ognized that various modifications are possible within the scope of the invention claimed.

I claim:

1. An apparatus for inspecting the quality of printing applied to successive printing areas on a continuously moving web, comprising means for scanning portions of said successive areas with the portions of any one area being scanned during a predetermined time interval and providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which, at the termination of said time interval, differs from its starting output, at the beginning of said interval, by an amount Which corresponds to the time integral of the sig nal obtained from all said portions of one area, means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area and providing a control signal indicative of whether the quantity of ink in the scanned area is intermediate or outside of said minimum and maximum tolerable quantities, and means for resetting said integrator means to its start condition after each of said time intervals.

2. An apparatus for inspecting the quality of printing applied to successive areas on a continuously moving web, comprising means for scanning with a light beam portions of said successive web areas with the portions of any one area being scanned during a predetermined time interval, means for controlling said light beam so that it has a range of wavelengths which is one of two wavelength ranges, one of said wavelength ranges being from about 0.7 to 1.0 micron and the other of said ranges comprising wavelengths from about 0.4 to 0.6 micron, said scanning means being adapted for providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which diifers from its starting output at the beginning of said interval by an amount 'which corresponds to the time integral of the signal obtained from all said portions of one area, means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities, and means for resetting said integrator means to its start condition after each of said time intervals.

3. An apparatus for inspecting the quality of printing applied to successive areas on a continuously moving Web, comprising means for scanning with a light beam portions of said successive areas with the portions of any one area being scanned during a predetermined time interval, means for controlling said light beam so that it has a range of wavelengths which is one of two wave length ranges, one of said wavelength ranges being from about 0.7 to 1.0 micron and the other of said ranges comprising Wavelengths from about 0.4 to 0.6 micron, said scanning means being adapted for providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which differs from its starting output at the beginning of said interval by an amount which corresponds to the time integral of the signal obtained from all said portions of one area, means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area and providing a control signal indicative of whether the quantity of ink in the scanned area is intermediate or outside of said minimum and maximum tolerable quantities, said integrator means including a capacitive load and means for providing a current to said capacitive load which is proportional to said signal, means for selectively varying the ratio of said current to said signal, and means for resetting said integrator means to its start condition after each of said time intervals.

4. An apparatus for inspecting the quality of printing applied to successive areas on a continuously moving web, comprising means for scannin mm a light beam portions of said successive areas with the portions of any one area being scanned during a predetermined time interval, means for controlling said light beam so that it has a range of wavelengths which is one of two wave length ranges, one of said wavelength ranges being from about 0.7 to 1.0 micron and the other of said ranges comprising wavelengths from about 0.4 to 0.6 micron, said scanning means being adapted for providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which differs from its start ing output at the beginning of said interval by an amount which corresponds to the time integral of the signal obtained from all said portions of one area, :said integrator means including a capacitive load and means for providing a current to said capacitive load which is proportional to said signal, means for selectively varying the ratio of said current to said sign-a1, comparator means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area, trigger means coupled with said comparator means and having two con ditions, one of said conditions being indicative of an integrator output outside of said reference signals and the other of said conditions being indicative of an integrator output intermediate said reference signals, means coupled to said trigger means for providing a control signal on the termination of said time interval representative of the condition of said trigger means, and means for resetting said integrator means to its start condition and for resetting said trigger means to a predetermined one of its two conditions after each of said time intervals.

5. An apparatus as set forth in claim 4 wherein said resetting means includes a delay circuit for delaying rer setting of said trigger means.

6. An apparatus for inspecting the quality of printing applied to successive areas on a continuously moving web, comprising means for scanning with a light beam portions of said successive areas with the portions of any one area being scanned during a predetermined time interval, means for controlling said light beam so that it has a range of wavelengths which is one of two wavelength ranges, one of said wavelength ranges being from about 0.7 to 1.0 micron and the other of said ranges comprising wavelengths from about 0.4 to 0.6 micron, said scanning means being adapted for providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which differs from its starting output at the beginning of said interval by an amount which corresponds to the time integral of the signal obtained from all said portions of one area, said integrator means including a semiconductor device having an emitter, a base and a collector, means for producing emitter current in said semiconductor device which is proportional to said signal, means for applying a bias voltage to said base, a capacitive load connected to said collector, means for selectively varying the ratio of said emitter current to said signal, comparator means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area, trigger means coupled with said comparator means and having two conditions, one of said conditions being indicative of an integrator output outside of said reference signals and the other of said conditions being indicative of an integrator output intermediate said reference signals, means coupled to said trigger means for providing a control signal on the termination of said time interval representative of the condition of said trigger means, and means for resetting said integrator means to its start condition and for resetting said trigger means to a predetermnied one of its two conditions after each of said time intervals.

7. An apparatus for inspecting the quality of printing applied -to successive areas on a continuously moving web, comprising means for scanning with a light beam portions of said successive areas with the portions of any one area being scanned during a predetermnied time interval, means for controlling said light beam so that it has a range of wavelengths which is one of two wavelength ranges, one of said wavelength ranges being from about 0.7 to 1.0 micron and the other of said ranges comprising wavelengths from about 0.4 to 0.6 micron, said scanning means being adapted for providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which differs from its starting output at the beginning of siad intervval by an amount which corresponds to the time integral of the signal obtained from said portions of one area, said integrator means including a semiconductor device having an emitter, a base and a collector, means for producing emitter current in said semiconductor device which is proportional to said signal, means for applying a bias voltage to said base, a capacitive load connected to said collector, means for selectively varying the ratio of said emitter current to said signal, comparator means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area, trigger means coupled with said comparator means and having two conditions, one of said conditions being indicative of an integrator output outside of said reference signals and the other of said conditions being indicative of an integrator output intermediate said reference signals, means coupled to said trigger means for providing a control signal on the termination of said time interval representative of the condition of said trigger means, means for resetting said integrator means to its start condition and for resetting said trigger means to a predetermined one of its two conditions after each of said time intervals, and said resetting means including normally nonconductive means connected to said collector and to said capacitive load, and means for rendering said normally nonconductive means conductive.

8. An apparatus for inspecting the quality of printing applied to successive areas on a continuously moving web, comprising means for scanning portions of said successive areas with the portions of any one area being scanned during a predetermined time interval and providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which diflers from its starting output at the beginning of said interval by an amount which corresponds to the time integral of the signal obtained from all said portions of one area, said integrator means including a first semiconductor device, an emitter, a base and a collector, means for producing emitter current in said first semiconductor device which is proportional to said signal and including a second semiconductor device having an emitter, a base and a collector, means coupling said second semiconductor device as a common collector stage between said scanning means and the emitter of said first semiconductor device, a capacitive load connected to the collector of said first semiconductor device, comparator means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area, trigger means coupled with said comparator means and having two conditions, one of said conditions being indicative of an integrator output outside of said reference signals and the other of said conditions being indicative of an integrator output intermediate said reference signals, means coupled to said trigger means for providing a control signal on the termination of said time interval representative of the condi tion of said trigger means, and means for resetting said integrator means to its start condition and for resetting said trigger means to a predetermined one of its two conditions after each of said time intervals.

9. An apparatus for inspecting the quality of printing applied to successive areas on a continuously moving web, comprising means for scanning portions of said successive areas with the portions of any one area being scanned during a predetermined time interval and providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which differs from its starting output at the beginning of said interval by an amount which corresponds to the time integral of the signal obtained from all said portions of one area, said integrator means including a first semiconductor device, an emitter, a base and a collector, means for producing emitter current in said first semiconductor device which is proportional to said Signal and including a second semiconductor device having an emitter, a base and a collector, means coupling said second semiconductor device as a common collector stage between said scanning means and the emitter of said first semiconductor device, a capacitive load connected to the collector of said first semiconductor device, comparator means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area, trigger means coupled with said comparator means and having two conditions, one of said conditions being indicative of an integrator output outside of said reference signals and the other of said conditions being indicative of an integrator output intermediate said reference signals, means coupled to said trigger means for providing a control signal on the termination of said time interval representative of the condition of said trigger means, means for resetting said integrator means to its start condition and for resetting said trigger means to a predetermined one of its two conditions after each of said time intervals, said resetting means including normally nonconductive means having one side thereof connected to the collector of said first semiconductor device and to one side of said capacitive load, a power stage including a semiconductor device connected to the other side of said capacitive load and to the other side of said normally nonconductive means, a driver stage coupled with said power stage and adapted when actuated to drive said power stage to conduct current, means for applying a reset pulse to said driver stage, said resetting means further including a delay means for delaying resetting of said trigger means.

10. An apparatus for inspecting the quality of printing applied to successive areas on a continuously moving web, comprising means for scanning portions of said successive areas with the portions of any one area being scanned during a predetermined time interval and providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which differs from its starting output at the beginning of said interval by an amount Which corresponds to the time integral of the signal obtained from all said portions of one area, said integrator means including a first semiconductor device, an emitter, a base and a collector, means connecting said first semiconductor device as a grounded base stage and for producing emitter current in said first semiconductor device which is proportional to said signal and including a second semiconductor device having an emitter, a base and a collector, means coupling said second semiconductor device as a common collector stage between said scanning means and the emitter of said first semiconductor device, a capacitive load connected to the collector of said first semiconductor device, comparator means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area, trigger means coupled with said comparator means and having two conditions, one of said conditions being indicative of an integrator output outside of said reference signals and the other of said conditions being indicative of an integrator output intermediate said reference signals, means coupled to said trigger means for providing a control signal on the termination of said time interval representative of the condition of said trigger means, and means for resetting said integrator means to its start condition and for resetting said trigger means to a predetermined one of its two conditions after each of said time intervals.

11. An apparatus for inspecting the quality of printing applied to successive areas on a continuously moving Web, comprising means for scanning portions of said successive areas with the portions of any one area being scanned during a predetermined time interval and providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which differs from its starting output at the beginning of said interval by an amount which corresponds to the time integral of the signal obtained from all said portions of one area, said integrator means including a first semiconductor device, an emitter, a base and a collector, means for producing emitter current in said first semiconductor device which is proportional to said signal and including a second semiconductor device having an emitter, a base and a collector, means coupling said second semiconductor device as a common collector stage between said scanning means and the emitter of said first semiconductor device, a capacitive load connected to the collector of said first semiconductor device, comparator means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area, buffer means for minimizing loading of said capacitive load and coupling said capacitive load with said comparator means, trigger means coupled with said comparator means and having two conditions, one of said conditions being indicative of an integrator output outside of said reference signals and the other of said conditions being indicative of an integrator output intermediate said reference signals, means coupled to said trigger means for providing a control signal on the termination of said time interval representative of the condition of said trigger means, and means for resetting said integrator means to its start condition and for resetting said trigger means to a predetermined one of its two conditions after each of said time intervals.

12. An integrator circuit, comprising a semiconductor device having an emitter, a base and a collector, means for coupling said semiconductor device to a source of a signal to be integrated over a predetermined time interval, means connecting said semiconductor device as a grounded base stage and for causing emitter current to flow which is proportional to said signal and for causing collector current to flow which is independent of collector voltage,

14 a capacitive load connected on one said collector, and connected on the other side thereof directly to a source of current at substantially fixed voltage and means connected to said capacitive load for restoring it to a predetermined condition as the start of each of said time intervals.

13. An integrator circuit, comprising a semiconductor device having an emitter, a base and a collector, means for coupling said semiconductor device to a source of a signal to be integrated over a predetermined time interval, means connecting said semiconductor device as a grounded base stage and for causing emitter current to flow which is proportional to said signal and for causing collector current to ilow which is independent of collector voltage, a capacitive load connected on one side thereof directly to said collector, and connected on the other side thereof directly to a source of current at substantially fixed voltage means for taking an output from across said capacitive load, and means for providing a path to the capacitive load only at the termination of said time interval and including normally nonconductive means con nected to said one side of said capacitive load and means for rendering said normally nonconductive means conductive only at the termination of said time interval.

14. An integrator circuit, comprising a first semiconductor device having an emitter, a base and a collector, means for coupling said first semiconductor device to a source of a signal to be integrated over a predetermined time interval and including a second semiconductor device connected as a common collector stage, means connecting said first semiconductor device as a grounded base stage and for causing in said first semiconductor device emitter current to flow which is proportional to said signal and for causing collector current to fiow which is independent of collector voltage, a capacitive load coupled on one side thereof with said collector, means for taking an output from across said capacitive load, and means for providing a path to the capacitive load only at the termination of said time interval and including normally nonconductive means connected to said one side of said capacitive side thereof directly to load and means for rendering said normally nonconductive means conductive only at the termination of said time interval.

15. A semiconductor integrator circuit, comprising a first semiconductor device having an emitter, a base and a collector, means for applying to said first semiconductor device a signal voltage variable between two extreme values, means for clamping one extreme value of said signal voltage at a predetermined value, a second semiconductor device having an emitter, a base and a collector, means coupling the collector of said first semiconductor device with the emitter of said second semiconductor device, a capacitive load having one side coupled with the collector of said second semiconductor device, a power stage connected to the other side of said capacitive load, driver means coupled with said power stage for driving the same to conduct, normally nonconductive means coupling said power stage with said one side of said capacitive load and providing, when conductive, a path for the capacitive load current, said normally nonconductive means being adapted to be rendered conductive when said power stage is conducting, and means for deriving an output from said capacitive load.

16. A semiconductor integrator circuit, comprising a first semiconductor device having an emitter, a base and a collector, means connecting said first semiconductor device as a common collector stage, means for applying to said base a signal voltage variable between two extreme values, means for clamping one extreme value of said signal voltage and of said base at a predetermined value, a second semiconductor device having an emitter, a base and a collector, means coupling the collector of said first semiconductor device with the emitter of said second semiconductor device, a capacitive load having one side coupled with the collector of said second semiconductor device, a power stage connected to the other side of said capacitive load, driver means coupled with said power stage for driving the same to conduct, normally nonconductive means coupling said power stage with said one side of said capacitive load and providing, when conductive, a path for the capacitive load current, said normally nonconductive means being adapted to be rendered conductive when said power stage is conducting, and means for deriving an output from said capacitive load.

17. A semiconductor integrator circuit, comprising a first semiconductor device having an emitter, a base and a collector, means connecting said first semiconductor device as a common collector stage, means for applying to said base a signal voltage variable between two extreme values,

means for clamping one extreme value of said signal voltage and of said base at a predetermined value, a second semiconductor device having an emitter, a base and a collector, means coupling the collector of said first semiconductor device with the emitter of said second semiconductor device, means for connecting said second semiconductor device as a grounded base stage, a capacitive load having one side coupled with the collector of said second semiconductor device, a power stage connected to the other side of said capacitive load, driver means coupled with said power stage for driving the same to conduct, normally nonconductive means coupling said power stage with said one side of said capacitive load and providing, when conductive, a path for the capacitive load current, said normally nonconductive means being adapted to be rendered conductive when said power stage is conducting, and means for deriving an output from said capacitive load.

18. A semiconductor integrator circuit, comprising first and second n-p-n type semiconductor devices, each having an emitter, a base and a collector, means coupling said semiconductor devices, said first semiconductor device being connected as a common collector stage and said second semiconductor device being connected as a grounded base stage, means for applying to the base of said first semiconductor device a signal to be integrated over a predetermined time interval, a capacitive load in the collector circuit of said second semiconductor device, mean for deriving an output from said capacitive load, said output being the time integral of said signal over said time interval, and means connected to said capacitive load for restoring it to a predetermined condition at the start of each of said time intervals.

19. An apparatus for inspecting the quality of printing applied to successive areas on a continuously moving web, comprising means for scanning with a light beam portions of said successive areas with the portions of any one area being scanned during a predetermined time interval, means for controlling said light beam so that it has a range of wavelengths which is one of two wavelength ranges, one of said wavelength ranges being from about 0.7 to 1.0 micron and the other of said ranges comprising wavelengths from about 0.4 to 0.6 micron, said scanning means being adapted for providing a signal which corresponds instantaneously to the reflectivity of the portion of said one area being scanned, means for integrating said signal during said time interval and providing an integrator output which differs from a predetermined condition at the beginning of said interval by an amount which corresponds to the time integral of the signal obtained from all said portions of one area, said integrator means including a semiconductor device having an emitter, a base and a collector, means for producing emitter current in said semiconductor device which is proportional to said signal, a capacitive load connected to said collector, comparator means for comparing said integrator output with reference signals representative of predetermined minimum and maximum tolerable quantities of ink in any one area, trigger means coupled with said comparator means and having two conditions, one of said conditions being indicative of an integrator output outside of said reference signals and the other of said conditions being indicative of an integrator output intermediate said reference signals, means coupled to said trigger means for providing a control signal on the termination of said time interval representative of the condition of said trigger means, means connected to said capacitive load for restoring it to said predetermined condition at the start of each of said time intervals, and means for resetting said trigger means to a predetermined one of its two conditions after each of said time intervals.

References Cited in the file of this patent UNITED STATES PATENTS 2,463,534 Hawkins Mar. 8, 1949 2,616,983 Zworykin et al Nov. 4, 1952 2,663,800 Herzog Dec. 22, 1953 2,674,916 Smith Apr. 13, 1954 2,787,717 Kasmir Apr. 2, 1957 2,798,966 Summerhayes July 9, 1957 2,863,065 De Witt et al. Dec. 2, 1958 2,894,058 Shapiro July 7, 1959 2,951,949 Kuntzleman et al. Sept. 6, 1960 UNITED STATES PATENT oEEieE CERTIFICATE OF CORRECTION Patent No. 3,056,032 Se1o'i;ember-:"25 1962 Maxwell R. Cannon It is hereby certified that error appears in the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column 6, line 63, before "transistor" insert type column 11, line 24, for predetermnied" read predetermined line 35, for "siad intervval" read said interval line 37, before "said", first occurrence insert all --5 column 14, line 5, for "as" read me at --Q Signed and sealed this 5th day of February 1963.

Attest:

ERNEST w. SWIDEE l)AVID LADD Attesting Officer Commissioner of Patents 

